In the present advanced information society, improvement in performance of solid-state memory devices formed using semiconductor integrated circuit technology has become essential. In particular, together with improvement in computational capability of Micro Processing Units (MPU) there has been a steady increase in memory capacity required for computers and electronic devices. Unlike magnetic and magneto optical storage devices such as hard disks, laser disks, and the like, since the solid-state memory devices do not have a physical driving part therein, the devices have a high mechanical strength and can be highly integrated based on semiconductor manufacturing technology. Therefore, the solid-state memory devices have been used not only as a temporary storage device (cache) or a main storage device (main memory) for a computer or a server, but also as an external storage device (storage memory) for a large number of mobile devices and domestic electrical appliances, and the present market is of the order of several tens of billions of dollars.
Such solid-state memory devices can be classified into three types according to their principle of operation: static random access memory (SRAM), dynamic random access memory (DRAM), and electrically erasable and programmable read only memory (EEPROM) represented by a flash memory device. Among these, the SRAM has the fastest operation, but it cannot retain information when power supply is stopped, and requires a large number of transistors for one bit, which is not suitable for providing a large capacity. Therefore, the SRAM is mainly used as a cache in an MPU. The DRAM requires refresh operations and operating speed is inferior to that of the SRAM; however, it can easily be integrated and unit cost per one bit is lower, so that it is principally used as a main memory for computers devices and household electrical appliances. On the other hand, the EEPROM is a non-volatile memory device capable of retaining information even while power supply is turned off; since the EEPROM speed is slower when writing and erasing information compared to the above two devices and requires relatively large electrical power, it is mainly used as storage memory.
With the rapid growth in the market for mobile devices in recent years, there has been anticipation for the development of a DRAM-compatible solid-state memory device that has higher speed and is capable of operating at a lower power consumption, and furthermore for the development of a nonvolatile solid-state memory device having features of both the DRAM and EEPROM. For such next-generation solid-state memory devices, an attempt has been made to develop a resistive random access (ReRAM) using a variable resistance material, and a ferroelectric RAM (FeRAM) using a ferroelectric substance. In addition, one promising candidate for a non-volatile memory device which has higher speed and is capable of operating at a lower power consumption is a resistance memory device that uses a phase change material, which is a variable resistance material as mentioned above, and this is referred to in particular as a phase change random access memory (PRAM). The phase change random access memory writes information at a very high speed, as high as about 50 ns, and has the advantage of being easy to integrate because of its simple device configuration.
The phase change random access memory is a nonvolatile memory device having a structure in which a phase change material is sandwiched between two electrodes, and the memory device is selectively operated by using an active element connected in series in a circuit. As the active element, for example, a MOS (metal-oxide-semiconductor) transistor, a junction diode, a bipolar transistor, a Schottky barrier diode, or the like, may be cited.
Storage and erasure of data in the phase change memory device are performed by using thermal energy to cause a transition between two or more solid phases, such as a (poly) crystal state and an amorphous state in a phase change material. The transition between the crystal state and the amorphous state is identified as change in a resistance value by a circuit connection through the electrodes. With regard to application of the thermal energy to the phase change material, an electrical pulse (voltage or current pulse) is applied between the electrodes to heat the phase change material itself by Joule heating. In this regard, for example, an electrical pulse of a large current is applied to a phase change material in a crystal state for a short time to heat the phase change material to a high temperature close to melting point and then cool it rapidly, to have an amorphous state (this state is referred to as a “reset state”). This operation is generally referred to as a reset operation. On the other hand, in the reset state, an electrical pulse of a current that is small in comparison with the reset operation is applied for a relatively long time, to heat the phase change material to the temperature of crystallization, to have a crystal state (this state is referred to as a “set state”). This operation is referred to as a set operation in contrast to the reset operation.
With regard to the phase change random access memory, there exist a vertical phase change memory device and a lateral phase change memory device.
The vertical phase change memory device is disclosed, for example, in Non-Patent Document 1. The vertical phase change memory device has a structure in which two electrodes in contact with phase change material are arrayed perpendicularly (vertically) with respect to the phase change material. In the vertical phase change memory device, a memory cell array is formed by arranging, in a lattice, cells combining phase change memory elements and select active elements. A feature of the vertical phase change memory device is that high integration is easy, and in addition, because of similarity to the structure of the DRAM, it is possible to use DRAM cell integration technology.
For example, Patent Document 1 describes one example of a layout of a DRAM having cell area of 6 F2. Here, F is a minimum processing dimension (a value of half of a word line spacing within a cell). In this layout, an active region is formed axisymmetrically, and word lines are wired in a Y direction at 1 F intervals. Cell contacts are formed in a central portion and on both side portions of the active region. After bit line contacts are formed directly above cell contacts of the central portion, the bit lines pass over the bit line contacts concerned, and extend in an X direction while meandering so as to avoid cell contacts at both side portions. Storage node contacts are formed on the cell contacts formed at both side portions of the active region. A central position of the storage node contacts is out of alignment with a central position of the cell contacts, and in this way, the storage node contacts are disposed to have equal spacing in an X direction. A storage capacitor is formed directly above the storage node contacts.
For the vertical phase change memory device it is possible to use a DRAM layout as described in Patent Document 1. Furthermore, by devising a configuration of memory cells and memory cell peripheral circuitry, according to the case, it is possible to also form a memory cell that does not have select active elements.
The lateral phase change memory device is disclosed, for example, in Non-Patent Document 2. In the lateral phase change memory device, two electrodes electrically connected to the phase change material are disposed laterally (on either side) to the phase change region in a planar form. Furthermore, an edge contact type also exists for the lateral phase change memory, as disclosed in Non-Patent Document 3.
[Patent Document 1]
    JP Patent Kokai Publication No. JP-P2007-287794A[Non-Patent Document 1]    Dae-Hwang Kim, et al., Simulation-based comparison of cell design concepts for phase change random access memory, Journal of Nanoscience and Nanotechnology, Vol. 7, pp. 298-305, 2007.[Non-Patent Document 2]    Martijn H. R. Lankhorst, et al., Low-cost and nanoscale non-volatile memory concept for future silicon chips, Nature Materials, Nature Publishing Group, Vol. 4, pp. 347-352, 2005.[Non-Patent Document 3]    Y. H Ha, et al., An edge contact type cell for phase change RAM featuring very low power consumption, 2003 Symposium on VLSI Technology, Digest of Technical Papers, 12B-4, pp. 175, 2003.